Typical analog fractional synthesizers are generally over-constrained in the design phase by shrinking processes, reduced supply voltage, and multi-standard integration. Essentially, digital phased locked loop (PLL) architectures, such as all-digital PLLs (ADPLLs), for example, as disclosed in [1-3], obviate to these limitations thanks to the intrinsically digital nature, with a digitally controlled oscillator (DCO) and a time-to-digital converter (TDC) as the sole analog blocks. As a result, ADPLLs offer wide programmability, easy technology scaling, and environmental robustness, while maintaining the same input-output behavior as analog PLLs. From a complexity standpoint, the “dividerless” architecture is most attractive because it mitigates the need for a critical multi-modulus divider by integrating the functions of Phase Frequency Detector—Charge Pump/dividers (PFD-CP/dividers) from a typical analog synthesizer into the TDC. An example, as disclosed in [5], of a dividerless architecture is depicted in FIG. 1. Another known, as disclosed in [6], dividerless architecture is depicted in FIG. 2.
In FIG. 1, Fref represents the reference clock, and Fout represents the ADPLL output signal. The frequency control word (FCW) defines the desired ratio between Fout and Fref. In FIG. 2, the TDC generates a digital word RDCO that represents the DCO output phase, and the word RR represents the reference phase.
Compared to a typical analog PLL, the divider, Phase Frequency Detector (PFD) and Charge Pump (CP) are all replaced by the TDC, which may provide a measurement of how the oscillator phase differs from the reference one. In particular, as shown in FIG. 1, the TDC computes the ratio between Fout and Fref, and an integrator INTEGRATOR converts the frequency error ε into a phase information, which corresponds to the phase difference between the output signal and the reference signal (except for a constant phase offset arising from integration). A low-pass digital filter DIGITAL LPF extracts the low-pass part of the output of the integrator, which is used to control the DCO.
In a practical application, however, the accuracy of such phase information is degraded by the finite reapproach of the TDC, which adds a quantization noise in the ADPLL loop.
The TDC depicted in FIG. 1 may comprise a simple clocked-resettable integer counter INTEGER COUNTER, characterized by a reapproach equal to a whole DCO period. Significantly better ADPLL performance can be achieved if a fractional counter FRACTIONAL COUNTER is used in conjunction with it, for improving the TDC reapproach while keeping the same dynamic range of the integer counter, as shown in FIG. 3. The digital output CF[n] of the fractional counter is derived by the block 1-z−1 and is added to the output CI[n] of the integer counter to generate the digital word Fout/Fref. The fractional counter is used to compute the residual time distance between two reference edges after integer counting, as illustrated in the time diagram of FIG. 4.
In this figure, the time interval Integer Count represents the result of integer counting operation (CI[n]), i.e. the number of DCO periods (periods of the continuous-time oscillating signal Fout) between two reference edges. The time interval Fractional Count (indicated in gray) is the result of the fractional counter computation (CF[n]), i.e. a measurement of the time distance between each reference edge and the last DCO edge. The residual time distance between two reference edges can be computed as CF[n]+(1−CF[n−1]), i.e. 1+(1-z−1)CF[n], as shown in FIG. 3 (where the constant contribution is not highlighted).
To illustrate why the fractional counter is useful, let us first consider the degenerate case where only an integer counter is used (and thus CF[n]=0). As an example, FIG. 5 depicts time graphs that show the synthesis of a fractional channel defined by FCW=120.2 starting from a 25 MHz reference, corresponding to a fractional frequency Ffrac=0.2*Fref=5 MHz.
As with a typical fractional PLL, when the ADPLL is locked, in correspondence with every reference edge, the distance between the last DCO (Fout) edge and the reference edge itself increases by 0.2*Tout. Tout is the period of the signal Fout due to non-integer frequency multiplication. Moreover, the average value of the integer counter may equal the FCW, such that the average value of ε[n] is zero.
Using an integer counter, in each group of 5 counts, as an average, only once the number 121 and four times the number 120 are attained (curve CI[n] in FIG. 5). This repeating sequence manifests itself periodically, so that a strong harmonic on ε[n] appears (curve (a)), the fundamental period of which is the fractional frequency Ffrac. By contrast, if a fractional counter with infinite precision were available, as in curves (b), ε[n] is identically 0, and thus, the TDC would add no quantization noise to the system.
In realistic cases, a fractional counter with temporal reapproach Tlsb is used, i.e. with K=Tout/Tlsb available quantization levels. As an example, let us consider the simple case with quantization levels of K=4. The corresponding CF[n] and ε[n] waveforms are reported in curves (c): the restriction to finite fractional counter reapproach has re-introduced harmonics in ε[n]. In particular, the larger the number of quantization levels, i.e. the better the TDC reapproach, the lower the output spurious tone level. Since the fundamental period of this sequence is related to the fractional frequency, spurious tones in the output at multiples of this frequency should be expected.
The preceding analysis shows that even with perfectly-spaced quantization levels, a TDC-based ADPLL may have spurious tones at the output arising from quantization error. In addition, it shows that the waveform of the sampled phase difference from the fractional counter is a ramp with period equal to the period of Ffrac. If this periodic ramp enters in a non-linear region of the characteristics of the TDC transfer function, spurious tones may be enhanced in the ADPLL output.
The generation of in band spurious tones, as disclosed in [4], is clearly visible in FIG. 6, at frequencies of about 106 Hz and 2·106 Hz. The amplitude of these tones is reduced by 30 dB in the reported figure compared to the real value, due to the use of a 1 kHz reapproach bandwidth for the measurement.
A potential drawback of these digital frequency synthesizers compared to the corresponding analog devices is that they suffer of relatively large in-band output spurious tones, which appear near the carrier at frequency offsets that are related to the periodicity in the TDC output pattern and are caused by the TDC finite reapproach. This phenomenon is further worsened by analog mismatches within the TDC.